Semiconductor devices

ABSTRACT

A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2020-0175579, filed on Dec. 15, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Devices,” is incorporated by reference herein in its entirety.

BACKGROUND 1. Field

Example embodiments relate to a semiconductor device. More particularly, example embodiments relate to a semiconductor device including transistors.

2. Description of the Related Art

A semiconductor device may include a plurality of transistors. The transistors included in the semiconductor device may have various structures according to required electrical performance, e.g., an operating voltage and/or driving currents. For example, an NMOS transistor and a PMOS transistor may have different stacked structures. For an isolation between NMOS transistors and an isolation between PMOS transistors, isolation structures may be formed at a substrate.

SUMMARY

According to example embodiments, there is provided a semiconductor device that may include a first trench formed at a substrate of a first region, a second trench formed at the substrate of a second region, a first isolation structure filling the first trench, a second isolation structure filling the second trench, a first gate structure formed on the substrate of the first region, and a second gate structure formed on the substrate of the second region. The first isolation structure may include a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked. The second isolation structure may include a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked. The first gate structure may include a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked. The second gate structure may include a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked. The first inner wall oxide pattern and the first liner may be conformally on a surface of the first trench. The first liner may protrude from upper surfaces of the first inner wall oxide pattern and the first filling insulation pattern. The second inner wall oxide pattern and the second liner may be conformally on a surface of the second trench. The second liner may protrude from upper surfaces of the second inner wall oxide pattern and the second filling insulation pattern.

According to example embodiments, there is provided a semiconductor device that may include a substrate including a cell array region, a first peripheral region, and a second peripheral region, memory cells on the substrate of the cell array region, trenches formed at the substrate of the first and second peripheral regions, an isolation structure filling each of the trenches, a channel layer on the substrate of the first peripheral region, a first gate structure formed on the channel layer, and a second gate structure formed on the substrate of the second peripheral region. The isolation structure may include an inner wall oxide pattern, a nitride liner, and a filling insulation pattern sequentially stacked. The channel layer may include silicon germanium. The first gate structure may include a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked. The second gate structure may include a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked. The inner wall oxide pattern and the nitride liner may be conformally on surfaces of the trenches. The nitride liner may protrude from upper surfaces of the inner wall oxide pattern and the filling insulation pattern.

According to example embodiments, there is provided a semiconductor device that may include a substrate including a cell array region, a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region, memory cells on the substrate of the cell array region, trenches at the substrate of the first to fourth peripheral regions, an isolation structure filling each of the trenches, a channel layer on the substrate of the first peripheral region, a first gate structure formed on the channel layer, a second gate structure formed on the substrate of the second peripheral region, a third gate structure formed on the substrate of the third peripheral region, and a fourth gate structure formed on the substrate of the fourth peripheral region. The isolation structure may include an inner wall oxide pattern, a nitride liner, and a filling insulation pattern sequentially stacked. The channel layer may include silicon germanium. The first gate structure may include a first interface insulation pattern, a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked. The second gate structure may include a second interface insulation pattern, a second high-k dielectric pattern, a second P-type metal pattern, and a second N-type metal pattern sequentially stacked. A thickness of the second interface insulation pattern may be greater than a thickness of the first interface insulation pattern, The third gate structure may include a third interface insulation pattern, a third high-k dielectric pattern, and a third N-type metal pattern sequentially stacked. The fourth gate structure may include a fourth interface insulation pattern, a fourth high-k dielectric pattern, and a fourth N-type metal pattern sequentially stacked. The nitride liner may be conformally on the surfaces of the trenches. The nitride liner may protrude from upper surfaces of the inner wall oxide pattern and the filling insulation pattern. Heights of uppermost surfaces of the nitride liners are substantially the same.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

FIG. 1 is a cross-sectional view of a semiconductor device in accordance with example embodiments;

FIG. 2 is a cross-sectional view of a semiconductor device in accordance with example embodiments;

FIG. 3 is a cross-sectional view of a semiconductor device in accordance with example embodiments;

FIGS. 4 to 16 are cross-sectional views of stages in a method of manufacturing a semiconductor device in accordance with example embodiments;

FIG. 17 is a cross-sectional view of a semiconductor device in accordance with example embodiments;

FIG. 18 is a cross-sectional view of a semiconductor device in accordance with example embodiments; and

FIGS. 19 to 26 are cross-sectional views of stages in a method of manufacturing a semiconductor device in accordance with example embodiments.

DETAILED DESCRIPTION

FIG. 1 is a cross-sectional view of a semiconductor device in accordance with example embodiments.

Referring to FIG. 1, a substrate 100 may include a first region A and a second region B. The substrate 100 may be, e.g., a single crystal silicon substrate or a silicon on insulator (SOI) substrate. The first region A may be a PMOS transistor region, and the second region B may be an NMOS transistor region.

A first trench 90 a may be formed in the substrate 100 in the first region A, and a second trench 90 b may be formed in the substrate 100 in the second region B. A first isolation structure 108 a may be formed in the first trench 90 a, and a second isolation structure 108 b may be formed in the second trench 90 b. In the substrate 100, a region in which the first and second isolation structures 108 a and 108 b are disposed may serve as a field region. A region of the substrate 100 between the first and second isolation structures 108 a and 108 b may serve as an active region.

The first isolation structure 108 a may include a first inner wall oxide pattern 102 a, a first liner 104 a, and a first filling insulation pattern 106 a. The first inner wall oxide pattern 102 a may be conformally formed on a surface of the first trench 90 a, and the first liner 104 a may be conformally formed on the first inner wall oxide pattern 102 a. The first filling insulation pattern 106 a may be formed on the first liner 104 a to fill the first trench 90 a.

The second isolation structure 108 b may include a second inner wall oxide pattern 102 b, a second liner 104 b, and a second filling insulation pattern 106 b. The second inner wall oxide pattern 102 b may be conformally formed on a surface of the second trench 90 b, and the second liner 104 b may be conformally formed on the second inner wall oxide pattern 102 b. The second filling insulation pattern 106 b may be formed on the second liner 104 b to fill the second trench 90 b.

The first and second inner wall oxide patterns 102 a and 102 b may be formed by the same deposition process, and thus the first and second inner wall oxide patterns 102 a and 102 b may include the same material. For example, the first and second inner wall oxide patterns 102 a and 102 b may include silicon oxide. The first liner 104 a and the second liner 104 b may be formed by the same deposition process, and thus the first liner 104 a and the second liner 104 b may include the same material. For example, the first liner 104 a and the second liner 104 b may include silicon nitride. The first and second filling insulation patterns 106 a and 106 b may be formed by the same deposition process, and thus the first and second filling insulation patterns 106 a and 106 b may include the same material. For example, the first and second filling insulation patterns 106 a and 106 b may include silicon oxide.

In example embodiments, a thickness (i.e., a thickness in a vertical direction from the surface of the trench) of the first inner wall oxide pattern 102 a may be greater than a thickness of the first liner 104 a. A thickness of the second inner wall oxide pattern 102 b may be greater than a thickness of the second liner 104 b.

In example embodiments, each of the first and second inner wall oxide patterns 102 a and 102 b may have the thickness of about 200 angstroms or more. For example, each of the first and second inner wall oxide patterns 102 a and 102 b may have a thickness of about 250 angstroms to about 400 angstroms. If the thickness of each of the first and second inner wall oxide patterns 102 a and 102 b is less than 200 angstroms, an inner width of each of first and second recessed portions 110 a and 110 b subsequently described may be decreased.

In the first isolation structure 108 a, the first liner 104 a may protrude from, e.g., above, upper surfaces of the first inner wall oxide pattern 102 a and the first filling insulation pattern 106 a. That is, an uppermost surface of the first liner 104 a may be higher than uppermost surfaces of the first inner wall oxide pattern 102 a and the first filling insulation pattern 106 a, e.g., relative to a bottom of the substrate 100. A first recessed portion 110 a may be formed, e.g., defined, between the first liner 104 a and the substrate 100 adjacent thereto. For example, as illustrated in FIG. 1, since the first liner 104 a and a portion of the substrate 100 (e.g., an impurity region 170 in a top portion of the substrate 100) protrude above the upper surface of the first inner wall oxide pattern 102 a from opposite sides thereof, the first recessed portion 110 a may be defined on the upper surface of the first inner wall oxide pattern 102 a between the protruding portions of the first liner 104 a and the substrate 100 (e.g., under dashed line in FIG. 1).

In example embodiments, the uppermost surface of the first filling insulation pattern 106 a may be substantially coplanar with the uppermost surface of the first inner wall oxide pattern 102 a, or may be lower than the uppermost surface of the first inner wall oxide pattern 102 a.

In example embodiments, the inner width of the first recessed portion 110 a, e.g., a distance between directly facing surfaces of the first liner 104 a and the substrate 100 along a horizontal direction parallel to the bottom of the substrate 100, may be greater than a height from a bottom of the first recessed portion 110 a to the uppermost surface of the first liner 104 a. In example embodiments, the bottom of the first recessed portion 110 a may be substantially flat, e.g., the upper surface of the first inner wall oxide pattern 102 a defining the bottom of the first recessed portion 110 a may be substantially flat. That is, a central portion of the bottom of the first recessed portion 110 a may not have a rounded shape, and the bottom of the first recessed portion 110 a may have a flat surface, e.g., an entire bottom surface of the first recessed portion 110 defined by the upper surface of the first inner wall oxide pattern 102 a may be level and parallel to the bottom surface of the substrate 100.

As such, an aspect ratio of the first recessed portion 110 a may be decreased, and the inner width of the first recessed portion 110 a may be increased. Therefore, metal layers deposited in the first recessed portion 110 a may be easily removed in processing for manufacturing the semiconductor device. Thus, the metal layers may not remain in the first recessed portion 110 a. Accordingly, defects (e.g., a bridge failure between gates) due to remains or residue of removed metal layers in the first recessed portion 110 a may be decreased.

The second isolation structure 108 b may have a shape and a structure similar to a shape and a structure of the first isolation structure 108 a. That is, in the second isolation structure 108 b, the second liner 104 b may protrude from, e.g., above, upper surfaces of the second inner wall oxide pattern 102 b and the second filling insulation pattern 106 b. The uppermost surface of the second liner 104 b may be higher than the uppermost surfaces of the second inner wall oxide pattern 102 b and the second filling insulation pattern 106 b, so a second recessed portion 110 b may be formed between the second liner 104 b and the substrate 100 adjacent thereto. In example embodiments, the uppermost surface of the second filling insulation pattern 106 b may be substantially coplanar with the uppermost surface of the second inner wall oxide pattern 102 b, or may be lower than the uppermost surface of the second inner wall oxide pattern 102 b.

In example embodiments, the inner width of the second recessed portion 110 b may be greater than a height from a bottom of the second recessed portion 110 b to the uppermost surface of the second liner 104 b. In example embodiments, the bottom of the second recessed portion 110 b may be substantially flat. That is, a central portion of the bottom of the second recessed portion 110 b may not have a rounded shape, and the bottom of the second recessed portion 110 b may have a flat surface.

In example embodiments, in the first and second isolation structures 108 a and 108 b, heights (e.g., vertical levels relative to the bottom of the substrate 100) of the uppermost surfaces of the first and second liners 104 a and 104 b including silicon nitride may be substantially the same. For example, in the first and second isolation structures 108 a and 108 b, the uppermost surfaces of the first and second liners 104 a and 104 b including silicon nitride may be substantially coplanar with an upper surface of a portion of the substrate adjacent to the first and second liners 104 a and 104 b.

In example embodiments, the uppermost surface of the first inner wall oxide pattern 102 a may be lower than the upper surface of the substrate 100 adjacent to the first trench 90 a, and the uppermost surface of the second inner wall oxide pattern 102 b may be lower than the upper surface of the substrate 100 adjacent to the second trench 90 b. The uppermost surface of the first inner wall oxide pattern 102 a and the uppermost surface of the second inner wall oxide pattern 102 b may be substantially coplanar with each other.

In example embodiments, a vertical level of the bottom of the second recessed portion 110 b may be substantially the same as a vertical level of the bottom of the first recessed portion 110 a. Further, a height of a protruding portion of the first liner 104 a may be substantially the same as a height of a protruding portion of the second liner 104 b.

A channel layer 130 may be formed on the substrate 100 of the first region A. A lattice constant of the channel layer 130 may be greater than a lattice constant of the substrate 100. For example, the channel layer 130 may include silicon germanium.

Hole mobility of a PMOS transistor formed on the channel layer 130 may be increased by the channel layer 130. Further, a threshold voltage of the PMOS transistor may be controlled by controlling a work function of the channel layer 130. For example, the channel layer 130 may have a low work function, so that the PMOS transistor may have a target threshold voltage. A first gate structure 160 may be formed on the channel layer 130.

First impurity regions 170 serving as first source/drain regions may be formed at the channel layer 130 and the substrate 100 adjacent to both sides of the first gate structure 160. The first impurity regions 170 may be doped with impurities, e.g., P-type impurities.

A second gate structure 162 may be formed on the substrate 100 of the second region B. Second impurity regions 172 serving as second source/drains may be formed in the substrate 100 adjacent to both sides of the second gate structure 162. The second impurity regions 172 may be doped with impurities, e.g., N-type impurities.

The first gate structure 160 may include a first interface insulation pattern, a first high-k dielectric pattern 140 a, a first P-type metal pattern 143, a first N-type metal pattern 144 a, a first lower electrode 146 a, a first barrier pattern 148 a, a first upper electrode 150 a, and a first capping layer pattern 152 a sequentially stacked. The second gate structure 162 may include a second interface insulation pattern, a second high-k dielectric pattern 140 b, a second N-type metal pattern 144 b, a second lower electrode 146 b, a second barrier pattern 148 b, a second upper electrode 150 b, and a second capping layer pattern 152 b sequentially stacked.

That is, the first gate structure 160 may include the first P-type metal pattern 143 and the first N-type metal pattern 144 a sequentially stacked, while the second gate structure 162 may include the second N-type metal pattern 144 b (i.e., without a p-type metal pattern). Except for stacking of the P-type metal pattern and the N-type metal pattern, stacked structures of the first and second gate structures 160 and 162 may be the same.

As the P-type metal pattern is not included in the second gate structure 162, a thickness of the first gate structure 160 may be greater than a thickness of the second gate structure 162, e.g., in the vertical direction along a normal to the bottom of the substrate 100. That is, the first gate structure 160 may have a first thickness, and the second gate structure 162 may have a second thickness less than the first thickness.

The first and second interface insulation patterns may include, e.g., silicon oxide or silicon oxynitride. The first high-k dielectric pattern 140 a and the second high-k dielectric pattern 140 b may include a metal oxide having a dielectric constant higher than a dielectric constant of silicon oxide. For example, The first high-k dielectric pattern 140 a and the second high-k dielectric pattern 140 b may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide, (LaAlO), zirconium oxide (ZrO), Zirconium silicate (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al₂O₃), and lead scandium tantalum oxide (PbScTaO). For example, the first and second high-k dielectric patterns 140 a and 140 b may include HfO₂, Al₂O₃, HfAlO₃, Ta₂O₃, or TiO₂.

The first P-type metal pattern 143 may include a metal material having P-work function. In example embodiments, the first P-type metal pattern 143 may include at least one of aluminum, aluminum oxide, titanium nitride, tungsten nitride, and ruthenium oxide. For example, the first P-type metal pattern 143 may include a stacked structure including a titanium nitride layer, an aluminum layer, and a titanium nitride layer or a stacked structure including a titanium nitride layer, an aluminum oxide layer, and a titanium nitride layer.

The first N-type metal pattern 144 a and the second N-type metal pattern 144 b may include a metal having an N-work function. In example embodiments, the N-type metal pattern 25 may include at least one of lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), and titanium nitride (TiN). For example, each of the first and second N-type metal patterns 144 a and 144 b may include a stacked structure including a lanthanum layer and a titanium nitride layer or a stacked structure including a lanthanum oxide layer and a titanium nitride layer.

The first lower electrode 146 a and the second lower electrode 146 b may include polysilicon doped with impurities. The first lower electrode 146 a may be doped with P-type impurities, and the second lower electrode 146 b may be doped with N-type impurities.

The first and second barrier patterns 148 a and 148 b may include, e.g., titanium nitride, tungsten nitride, or tantalum nitride.

The first upper electrode 150 a and the second upper electrode 150 b may include a metal. The first upper electrode 150 a may include, e.g., a metal silicide layer, a metal nitride layer, or a metal layer. The metal silicide may include, e.g., cobalt silicide or tungsten silicide. The metal nitride layer may include, e.g., a titanium nitride layer or a tantalum nitride layer. The metal layer may include, e.g., tungsten.

The first and second capping layer patterns 152 a and 152 b may include, e.g., silicon nitride. A first spacer 164 may be formed on a sidewall of the first gate structure 160. A second spacer 166 may be formed on a sidewall of the second gate structure 162. The first and second spacers 164 and 166 may include, e.g., silicon oxide and/or silicon nitride.

In the semiconductor device, the first and second isolation structures 108 a and 108 b may include first and second liners 104 a and 104 b having protruding portions, respectively, that define first and second recessed portions 110 a and 110 b adjacent to the first and second gate structures 160 and 162, respectively. However, during manufacturing, metal material may not remain in the first and second recessed portions 110 a and 110 b due to increased width thereof. Therefore, in the semiconductor device, potential defects caused by residual metal materials in the first and second recessed portions 110 a and 110 b may be decreased.

FIG. 2 is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments. The semiconductor device in FIG. 2 is substantially the same as the semiconductor device described with reference to FIG. 1, except for shapes of the first and second isolation structures.

Referring to FIG. 2, a bottom of each of the first and second recessed portions 110 a and 110 b may have a slope with respect to a flat upper surface of the substrate 100, e.g., the bottom of each of the first and second recessed portions 110 a and 110 b may be inclined at an oblique angle with respect to the bottom of the substrate 100. A central portion of the bottom of each of the first and second recessed portions 110 a and 110 b may not have a rounded shape.

In example embodiments, an uppermost surface of the first filling insulation pattern 106 a may be substantially coplanar with an upper surface of the first inner wall oxide pattern 102 a, or may be lower than the upper surface of the first inner wall oxide pattern 102 a. In example embodiments, an uppermost surface of the second filling insulation pattern 106 b may be substantially coplanar with an upper surface of the second inner wall oxide pattern 102 b, or may be lower than the upper surface of the second inner wall oxide pattern 102 b.

FIG. 3 is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments. The semiconductor device in FIG. 3 is substantially the same as the semiconductor device described with reference to FIG. 1, except for shapes of the first and second isolation structures.

Referring to FIG. 3, a width of the first filling insulation pattern 106 a, e.g., as measured between directly facing surfaces of the first liner 104 a, may be greater than a width of the first inner wall oxide pattern 102 a. In example embodiments, the width of the first filling insulation pattern 106 a may be greater than twice the width of the first inner wall oxide pattern 102 a. The width of the first inner wall oxide pattern 102 a may be a thickness of the first inner wall oxide pattern 102 a in the vertical direction from a sidewall of the first trench 90 a, e.g., the width of the first inner wall oxide pattern 102 a may be a distance between directly facing surfaces of the first inner wall oxide pattern 102 a and the sidewall of the first trench 90 a along a horizontal direction parallel to the bottom of the substrate 100.

When the width of the first filling insulation pattern 106 a is greater than the width of the first inner wall oxide pattern 102 a, the first filling insulation pattern 106 a may be easily exposed to an etching gas during an etching process. Thus, an amount of etching of the first filling insulation pattern 106 a may increase, so that an uppermost surface of the first filling insulation pattern 106 a may be lower than an uppermost surface of the first inner wall oxide pattern 102 a, e.g., relative to the bottom of the substrate 100.

A width of the second filling insulation pattern 106 b may be greater than a width of the second inner wall oxide pattern 102 b. In this case, an uppermost surface of the second filling insulation pattern 106 b may be lower than an uppermost surface of the second inner wall oxide pattern 102 b. In example embodiments, the width of the second filling insulation pattern 106 b may be greater than twice the width of the second inner wall oxide pattern 102 b.

FIGS. 4 to 16 are cross-sectional views of stages in a method of manufacturing a semiconductor device in accordance with example embodiments.

Referring to FIG. 4, the substrate 100 may include the first region A and the second region B. A portion of the substrate 100 may be etched to form the first and second trenches 90 a and 90 b. The first trench 90 a may be formed in a portion of the substrate 100 of the first region A, and the second trench 90 b may be formed in a portion of the substrate 100 of the second region B.

An inner wall oxide layer may be conformally formed on an upper surface of the substrate 100 and surfaces of the first and second trenches 90 a and 90 b. A liner layer may be formed on the inner wall oxide layer. The inner wall oxide layer may be formed to have a thickness greater than a thickness of the liner layer. The inner wall oxide layer may have a thickness of 200 angstroms or more, e.g., the inner wall oxide layer may have a thickness of about 250 angstroms to about 400 angstroms.

In example embodiments, the inner wall oxide layer may include silicon oxide. The inner wall oxide layer may be formed by a thermal oxidation process and/or a deposition process. In example embodiments, the liner layer may include silicon nitride. The liner layer may be formed by a deposition process.

A filling insulation layer may be formed on the liner layer to fill the first and second trenches 90 a and 90 b. The filling insulation layer may include silicon oxide. The filling insulation layer may be formed by a deposition process.

Thereafter, the filling insulation layer, the liner layer, and the inner wall oxide layer may be planarized until an upper surface of the substrate 100 is exposed to form a preliminary first isolation structure 107 a and a preliminary second isolation structure 107 b. The preliminary first isolation structure 107 a may be formed in the first trench 90 a, and the preliminary second isolation structure 107 b may be formed in the second trench 90 b.

The preliminary first isolation structure 107 a may include a preliminary first inner wall oxide pattern 101 a, the first liner 104 a, and a preliminary first filling insulation layer pattern 105 a. The preliminary second isolation structure 107 b may include a preliminary second inner wall oxide pattern 101 b, the second liner 104 b, and a preliminary second filling insulation layer pattern 105 b.

Referring to FIG. 5, a first mask layer 120 may be formed to cover the substrate 100 and the preliminary first and second isolation structures 107 a and 107 b. The first mask layer 120 may be a silicon oxide layer. For example, the first mask layer 120 may include TEOS (Tetra Ethyl Ortho Silicate) material.

A first photoresist pattern 122 may be formed on the first mask layer 120. The first photoresist pattern 122 may cover the second region B, and may expose the first region A.

Referring to FIG. 6, the first mask layer may be etched using the first photoresist pattern 122 as an etching mask to form a first mask pattern 120 a. The etching process of the first mask layer may include a wet etching process. When the wet etching process is performed, etching damages applied to the surface of the substrate 100 may be decreased. Thereafter, the first photoresist pattern 122 may be removed.

As the first mask layer includes silicon oxide, a silicon oxide layer may be etched in the etching process for forming the first mask pattern 120 a. In the etching process for forming the first mask pattern 120 a, a layer positioned below an etched first mask pattern 120 a may be overetched, and thus a silicon oxide layer of an upper portion of the preliminary first isolation structure 107 a may be etched together.

Therefore, upper portions of the preliminary first inner wall oxide pattern 101 a and the preliminary first filling insulation layer pattern 105 a included in the preliminary first isolation structure 107 a may be partially etched to form the first isolation structure 108 a. The first isolation structure 108 a may include the first inner wall oxide pattern 102 a, the first liner 104 a, and the first filling insulation pattern 106 a.

In the first isolation structure 108 a, an upper surface of the first inner wall oxide pattern 102 a may be lower than an upper surface of the first liner 104 a, so that the first recessed portion 110 a may be formed between the first liner 104 a and the substrate 100 adjacent thereto. The substrate 100 of the first region A and an upper surface of the first isolation structure 108 a may be exposed by the first mask pattern 120 a.

In example embodiments, an etching thickness in the vertical direction of the preliminary first inner wall oxide pattern 101 a may be less than a depositing thickness (i.e., a depositing thickness in the vertical direction from a sidewall of the first trench 90 a) of the inner wall oxide layer. In example embodiments, an inner width of the first recessed portion 110 a may be greater than a height from a bottom of the first recessed portion 110 a to an uppermost surface of the first liner 104 a.

As the first liner 104 a includes silicon nitride, the first liner 104 a may be hardly removed in the etching process. Thus, the uppermost surface of the first liner 104 a may be substantially coplanar with the upper surface of the substrate 100 adjacent to the first liner 104 a.

In example embodiments, an upper portion, e.g., an uppermost surface, of the first liner 104 a may have a rounded shape, after the etching process. Further, an edge of the active region of the substrate 100 may have a rounded shape, after the etching process.

The first liner 104 a may protrude from, e.g., above, upper portions of the first inner wall oxide pattern 102 a and the first filling insulation pattern 106 a. That is, the uppermost surface of the first liner 104 a may be higher than the uppermost surfaces of the first inner wall oxide pattern 102 a and the first filling insulation pattern 106 a.

In example embodiments, a bottom of the first recessed portion 110 a may have a flat surface. As the inner width of the first recessed portion 110 a is increased, a central portion of the bottom of the first recessed portion 110 a may not have a rounded shape. The central portion of the bottom of the first recessed portion 110 a may have a flat surface. In some example embodiments, as shown in FIG. 2, the bottom of the first recessed portion 110 a may have a slope with respect to the upper flat surface of the substrate.

Referring to FIG. 7, the channel layer 130 may be formed on the upper surface of the substrate 100 of the first region exposed by the first mask pattern 120 a. The channel layer 130 may be formed by, e.g., a selective epitaxial growth process (SEG). The channel layer 130 may include silicon germanium. The channel layer 130 may be selectively formed on the substrate 100 for forming a PMOS transistor.

Referring to FIG. 8, a second photoresist pattern 124 may be formed on the channel layer 130 and the first isolation structure 108 a in the first region A. The second photoresist pattern 124 may cover the first region A, and may expose the second region B.

The first mask pattern 120 a in the second region B may be selectively exposed by the second photoresist pattern 124. The channel layer 130 and the first isolation structure 108 a in the first region A may not be exposed by the second photoresist pattern 124.

Referring to FIG. 9, the first mask pattern 120 a may be removed using the second photoresist pattern 124 as an etching mask. The removing process of the first mask pattern 120 a may include a wet etching process.

As the first mask pattern 120 a includes silicon oxide, a silicon oxide layer may be etched in the removing process of the first mask pattern 120 a. In the removing process of the first mask pattern 120 a, a silicon oxide layer positioned below a removed first mask pattern 120 a may be overetched, and thus a silicon oxide layer of an upper portion of the preliminary second isolation structure 107 b may be etched together.

Therefore, upper portions of the preliminary second inner wall oxide pattern 101 b and the preliminary second filling insulation layer pattern 105 b included in the preliminary second isolation structure 107 b may be partially etched to form the second isolation structure 108 b. However, as the second liner 104 b includes silicon nitride, the second liner 104 b may be hardly removed during the removing process.

The second isolation structure 108 b may include the second inner wall oxide pattern 102 b, the second liner 104 b, and the second filling insulation pattern 106 b. The second liner 104 b may protrude from, e.g., above, upper portions of the second inner wall oxide pattern 102 b and the second filling insulation pattern 106 b. That is, the uppermost surface of the second liner 104 b may be higher than uppermost surfaces of the second inner wall oxide pattern 102 b and the second filling insulation pattern 106 b. The second recessed portion 110 b may be formed between the second liner 104 b and the substrate 100 adjacent thereto.

In example embodiments, in the removing process, a vertical level of a bottom of the second recessed portion 110 b may be substantially the same as a vertical level of the bottom of the first recessed portion 110 a. In example embodiments, a height of a protruding portion of the first liner 104 a may be substantially the same as a height of a protruding portion of the second liner 104 b.

In example embodiments, the second liner 104 b may be hardly etched during the etching processes, so that the uppermost surface of the second liner 104 b may be substantially coplanar with an upper surface of the substrate adjacent to the second liner 104 b. Upper surfaces of the first and second liners 104 a and 104 b may be substantially coplanar with each other.

In example embodiments, an inner width of the second recessed portion 110 b may be greater than a height from a bottom of the second recessed portion 110 b to an uppermost surface of the second liner 104 b. In example embodiments, the bottom of the second recessed portion 110 b may be substantially flat. That is, the central portion of the bottom of the second recessed portion 110 b may not have a rounded shape, and the bottom of the second recessed portion 110 b may have a flat surface. In some embodiments, as shown in FIG. 2, the bottom of the second recessed portion 110 b may have a slope with respect to the flat upper surface of the substrate 100.

As the second photoresist pattern 124 may be formed, a silicon oxide layer positioned at the first region A may not be removed during the removing process of the first mask pattern 120 a. In the removing process of the first mask pattern 120 a, layers included in the first isolation structure 108 a may not be removed, so that a shape of the first isolation structure 108 a may not change. Thereafter, the second photoresist pattern 124 may be removed.

Referring to FIG. 10, a first interface insulation layer may be formed on the channel layer 130 of the first region A, and a second interface insulation layer may be formed on the substrate 100 of the second region B. The first and second interface insulation layers may be formed by a thermal oxidation process and/or a deposition process. The first and second interface insulation layers may be formed of, e.g., a silicon oxide layer and/or a silicon oxynitride layer.

A high-k dielectric layer 140 may be conformally formed on the first interface insulation layer, the second interface insulation layer, and the first and second isolation structures 108 a and 108 b. A P-type metal layer 142 may be conformally formed on the high-k dielectric layer 140. The P-type metal layer 142 may be formed not to completely fill the first and second recessed portions 110 a and 110 b, and the P-type metal layer 142 may be formed along sidewalls and bottoms of the first and second recessed portions 110 a and 110 b. Thus, after forming the P-type metal layer 142, each of the first and second recessed portions 110 a and 110 b may have remaining inner space.

The P-type metal layer 142 may include a metal layer having a P-work function. In example embodiments, the P-type metal layer 142 may include at least one of aluminum (Al), aluminum oxide, titanium nitride (TiN), tungsten nitride (WN), and ruthenium oxide (RuO₂). For example, the P-type metal layer 142 may include a stacked structure including a titanium nitride layer, an aluminum layer, and a titanium nitride layer or a stacked structure including a titanium nitride layer, an aluminum oxide layer, and a titanium nitride layer.

Referring to FIG. 11, a third mask pattern 132 may be formed on the P-type metal layer 142. The third mask pattern 132 may cover the first region A, and may expose the second region B. The third mask pattern 132 may include at least one of a photoresist, an amorphous carbon layer (ACL), a spin on hardmask (SOH), a spin on carbon (SOC), and a silicon nitride layer.

Referring to FIG. 12, the P-type metal layer 142 of the second region B may be etched using the third mask pattern 132 as an etching mask so as to expose the high-k dielectric layer 140. The P-type metal layer 142 may only remain in the first region A, and thus a preliminary P-type metal layer pattern 142 a may be formed in the first region A. The process of etching the P-type metal layer 142 may include a wet etching process. As the wet etching process may be performed, etching damages of the high-k dielectric layer 140 may be decreased compared to performing a dry etching process.

The third mask pattern 132 may be removed. Thereafter, an N-type metal layer 144 may be conformally formed over entire surface of the substrate 100.

The N-type metal layer 144 may include a metal having an N-work function. In example embodiments, the N-type metal layer 144 may include at least one of lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), and titanium nitride (TiN). For example, the N-type metal layer 144 may include a stacked structure including a lanthanum layer and a titanium nitride layer or a stacked structure including a lanthanum oxide layer and a titanium nitride layer.

FIGS. 13 and 14 are enlarged views of portion “F” of FIG. 12.

Referring to FIG. 13, the bottom of the first recessed portion 110 a may be substantially flat. In this case, after forming the preliminary P-type metal layer pattern 142 a and the N-type metal layer 144, the first recessed portion 110 a may have a remaining inner space.

Referring to FIG. 14, the bottom of the first recessed portion 110 a may have a slope with respect to the flat upper surface of the substrate 100. In this case, after forming the preliminary P-type metal layer pattern 142 a and the N-type metal layer 144, the first recessed portion 110 a may have a remaining inner space.

Referring back to FIG. 12, after forming the N-type metal layer 144, the second recessed portion 110 b may have remaining inner space. In example embodiments, a width of the inner space of each of the first and second recessed portions 110 a and 110 b may be greater than a sum of thicknesses of the layers formed on the upper sidewall of the first trench 90 a exposed by the first recessed portion 110 a. For example, referring to FIGS. 13 and 14, the width of the inner space of each of the first and second recessed portions 110 a and 110 b may be greater than a sum of thicknesses of the first interface insulation layer 138, the high-k dielectric layer 140, the preliminary P-type metal layer pattern 142 a, and the N-type metal layer 144.

Referring to FIG. 15, a lower electrode layer 146, a barrier layer 148, an upper electrode layer 150, and a capping layer may be sequentially stacked on the N-type metal layer 144. The capping layer may be patterned to form the capping layer pattern 152.

The lower electrode layer 146 may be formed of a polysilicon layer doped with impurities. Particularly, for forming the lower electrode layer 146, the polysilicon layer may be deposited on the N-type metal layer 144. Thereafter, the polysilicon layer positioned on the first region A may be doped with P-type impurities, and the polysilicon layer positioned on the second region B may be doped with N-type impurities. In example embodiments, the lower electrode layer 146 may be formed to fill the first and second recessed portions 110 a and 110 b.

The barrier layer 148 may be formed of, e.g., a titanium nitride layer, a tungsten nitride layer, or a tantalum nitride layer. The upper electrode layer 150 may include a metal material, e.g., tungsten. The capping layer pattern 152 may include, e.g., silicon nitride.

Referring to FIG. 16, the upper electrode layer 150, the barrier layer 148, the lower electrode layer 146, the N-type metal layer 144, a preliminary P-type metal layer pattern 142 a, the high-k dielectric layer 140, and the first and second interface insulation layers may be sequentially etched using the capping layer pattern 152 as an etching mask to form the first gate structure 160 in the first region A and the second gate structure 162 in the second region B. The etching process may include an anisotropic etching process.

The first gate structure 160 may include a first interface insulation pattern, the first high-k dielectric pattern 140 a, the first P-type metal pattern 143, the first N-type metal pattern 144 a, the first lower electrode 146 a, the first barrier pattern 148 a, the first upper electrode 150 a, and the first capping layer pattern 152 a stacked. The second gate structure 162 may include a second interface insulation pattern, the second high-k dielectric pattern 140 b, the second N-type metal pattern 144 b, the second lower electrode 146 b, the second barrier pattern 148 b, the second upper electrode 150 b, and the second capping layer pattern 152 b stacked.

In the etching process, it is required that both the preliminary P-type metal layer pattern 142 a and the N-type metal layer 144 formed in the first and second recessed portions 110 a and 110 b are completely removed. If the inner widths of the first and second recessed portions 110 a and 110 b were to be narrow, etching gases would not have easily flown into the first and second recessed portions 110 a and 110 b, thereby causing the preliminary P-type metal layer pattern 142 a and the N-type metal layer 144 to partially remain in the first and second recessed portions 110 a and 110 b, which in turn, would have generated defects by residues of the preliminary P-type metal layer pattern 142 a and the N-type metal layer 144.

In contrast, according to example embodiments, after forming the preliminary P-type metal layer pattern 142 a and the N-type metal layer 144, each of the first and second recessed portions 110 a and 110 b may maintain sufficient inner space, e.g., due to their larger width. Therefore, the etching gases for etching the metal materials may easily and sufficiently flow into the first and second recessed portions 110 a and 110 b, so that both the preliminary P-type metal layer pattern 142 a and the N-type metal layer 144 positioned in the first and second recessed portions 110 a and 110 b may be completely removed.

Further, if the inner widths of the first and second recessed portions 110 a and 110 b were to be narrow, the bottom of the first and second recessed portions 110 a and 110 b would have had a rounded shape. In this case, the metal layer would have been formed to have a relatively thick thickness in lower portions having the round portions of the first and second recessed portions 110 a and 110 b, so that the metal layer would have filled the lower portions of the first and second recessed portions 110 a and 110 b. A thickness in the vertical direction of the metal layer formed on the bottoms of the first and second recessed portion would have increased, thereby making removal of the metal layer from the bottoms of the first and second recessed portions 110 a and 110 b difficult.

In contrast, according to example embodiments, as the bottoms of the first and second recessed portions 110 a and 110 b have flat surfaces, the N-type metal layer 144 and the preliminary P-type metal layer pattern 142 a may not be folded at the bottoms of the first and second recessed portions 110 a and 110 b. The N-type metal layer 144 and the preliminary P-type metal layer pattern 142 a formed on the bottom of the first and second recessed portions 110 a and 110 b may have flat surfaces. Thus, metal layers formed on the bottom of the first and second recessed portions 110 a and 110 b may be easily removed.

Referring to FIG. 1 again, the first spacer 164 may be formed on a sidewall of the first gate structure 160, and the second spacer 166 may be formed on a sidewall of the second gate structure 162. P-type impurities may be implanted onto the substrate 100 adjacent to both sides of the first gate structure 160 to form the first impurity regions 170. N-type impurities may be implanted onto the substrate 100 adjacent to both sides of the second gate structure 162 to form the second impurity regions 172.

As described above, a semiconductor device having high reliability may be manufactured.

FIG. 17 is a cross-sectional view of a semiconductor device in accordance with example embodiments.

Referring to FIG. 17, the substrate 100 may include a cell array region CA, a first peripheral region A1, a second peripheral region A2, a third peripheral region B1, and a fourth peripheral region B2. The first to fourth peripheral regions A1, A2, B1, and B2 may be disposed around the cell array region CA. Peripheral circuits for driving cells formed in the cell array region CA may be formed in the first to fourth peripheral regions A1, A2, B1, and B2.

A low voltage PMOS transistor may be formed in the first peripheral region A1. A high voltage PMOS transistor may be formed in the second peripheral region A2. A low voltage NMOS transistor may be formed in the third peripheral region B1. A high voltage NMOS transistor may be formed in the fourth peripheral region B2.

Memory cells may be formed in the cell array region CA. For example, the memory cells may include dynamic random-access memory (DRAM) cells.

A cell isolation structure 201 may be formed in a cell trench 92 at the substrate 100 of the cell array region CA. A portion of the substrate 100 of the cell array region CA, in which the cell isolation structure 201 is not formed, may be defined as cell active regions. Each of the cell active regions may have an isolated shape. In a plan view, each of the cell active regions may have an isolated bar shape. Each of the cell active regions may be arranged in a direction oblique to an extending direction of a word line. The substrate 100 may be a single crystal silicon substrate or an SOI substrate.

In the cell array region CA, a width of the cell trench 92 may vary according to a space between adjacent cell active regions, and a stacked structure of the cell isolation structure 201 filling the cell trench may also vary according to the width of the cell trench 92. In example embodiments, when the width of the cell trench 92 is narrow, the cell trench 92 may be completely filled with an inner wall oxide layer including silicon oxide. In this case, the cell isolation structure 201 may include only silicon oxide, in a cross sectional view.

In some example embodiments, the cell trench may be completely filled with an inner wall oxide layer and a nitride liner, according to the width of the cell trench. In this case, the cell isolation structure may include silicon oxide and silicon nitride, in a cross sectional view.

A buried word line may be formed in the cell active region and the cell isolation structure 201. The buried word line may extend in a first direction. Impurity regions may be formed at the substrate 100 adjacent to both sides of the word line in the cell active region.

A buffer layer 216 may be formed on the substrate 100 in the cell array region CA. In example embodiments, the buffer layer 216 may include a first insulation layer pattern 210, a second insulation layer pattern 212, and a third insulation layer pattern 214 sequentially stacked. The second insulation layer pattern 212 may include a material having a high etch selectivity with respect to the first and third insulation layer patterns 210 and 214. For example, the second insulation layer pattern 212 may be formed of a silicon nitride layer, and each of the first and third insulation layer patterns 210 and 214 may be formed of a silicon oxide layer. In some example embodiments, the buffer layer 216 may have a two-layer structure including a silicon oxide layer and a silicon nitride layer.

A bit line structure 280 may be formed on the buffer layer 216. The bit line structure 280 may extend in a second direction perpendicular to the first direction. The bit line structure 280 may include a lower electrode, an upper electrode, a barrier pattern, and a capping layer pattern sequentially stacked. In addition, a portion of the bit line structure 280 may contact the impurity region of the substrate 100.

The bit line structure 280 may be formed by the same deposition processes as the deposition processes for forming the first to fourth gate structures 260 a, 260 b, 260 c, and 260 d in the first to fourth peripheral regions A1, A2, B1, and B2, as will be described in detail below. Thus, the bit line structure 280 may include materials included in the first to fourth gate structures 260 a, 260 b, 260 c, and 260 d.

The lower electrode may include polysilicon doped with impurities. The upper electrode may include a metal, e.g., tungsten. The capping layer pattern may include silicon nitride.

A bit line spacer 282 may be formed on a sidewall of the bit line structure 280. An insulation layer may be formed to fill a space between adjacent bit line structures 280. The insulation layer may, e.g., silicon oxide.

Contact plugs 284 may pass through the insulation layer, and the contact plugs 284 may be formed between adjacent bit line structures 280. The contact plugs 284 may contact the surface of the substrate 100. In example embodiments, the contact plugs 284 may include a polysilicon pattern and a metal pattern stacked.

An upper insulation pattern 286 may be formed between the upper portions of the contact plugs 284. Upper portions of the contact plugs 284 may be electrically isolated by the upper insulation pattern 286.

A capacitor 290 may be formed on each of the contact plugs 284. The capacitor 290 may include a lower electrode 290 a, a dielectric layer 290 b, and an upper electrode 290 c stacked. In the capacitor 290, the lower electrode 290 a may have a cylindrical shape or a pillar shape.

In the first to fourth peripheral regions A1, A2, B1, and B2, isolation structures 208 a may be formed in trenches in the substrate 100, respectively. In the first to fourth peripheral regions A1, A2, B1, and B2, a region of the substrate 100 between the isolation structures 208 a may be defined as a peripheral active region.

The channel layer 130 may be formed on the substrate 100 of the first peripheral region A1. The channel layer 130 may be formed of, e.g., silicon germanium. A first gate structure 260 a may be formed on the channel layer 130. First impurity regions 264 a may be formed at the channel layer 130 adjacent to both sides of the first gate structure 260 a. The first impurity regions 264 a may be doped with P-type impurities.

A second gate structure 260 b may be formed on the substrate 100 of the second peripheral region A2. Second impurity regions 264 b may be formed at the substrate 100 adjacent to both sides of the second gate structure 260 b. The second impurity regions 264 b may be doped with P-type impurities.

A third gate structure 260 c may be formed on the third peripheral region B1. Third impurity regions 264 c may be formed at the substrate 100 adjacent to both sides of the third gate structure 260 c. The third impurity region 264 c may be doped with N-type impurities.

A fourth gate structure 260 d may be formed on the fourth peripheral region B2. Fourth impurity regions 264 d may be formed at the substrate 100 adjacent to both sides of the fourth gate structure 260 d. The fourth impurity regions 264 d may be doped with N-type impurities.

In example embodiments, each of the isolation structures 208 a formed in the first to fourth peripheral regions A1, A2, B1, and B2 may be substantially the same as the first and second isolation structures 108 a and 1098 b described with reference to FIG. 1. Each of the isolation structures 208 a formed in the first to fourth peripheral regions A1, A2, B1, and B2 may include an inner wall oxide pattern 202 a, a nitride liner 204 a, and a filling insulation pattern 206 a.

In the isolation structure 208 a, the nitride liner 204 a may protrude from upper portions of the inner wall oxide pattern 202 a and the filling insulation pattern 206 a. That is, an uppermost surface of the nitride liner 204 a may be higher than uppermost surfaces of the inner wall oxide pattern 202 a and the filling insulation pattern 206 a. A recessed portion 222 may be formed between the nitride liner 204 a and the substrate 100 adjacent to the nitride liner 204 a.

In example embodiments, an inner width of the recessed portion 222 may be greater than a height from a bottom of the recessed portion 222 to an uppermost surface of the nitride liner 204 a. In example embodiments, the bottom of the recessed portion 222 may have a flat surface. That is, the central portion of the bottom of the recessed portion 222 may not have a rounded shape, and may have a flat surface.

In example embodiments, in the isolation structures 208 a in the first to fourth peripheral regions A1, A2, B1 and B2, heights (i.e., vertical levels) of the uppermost surfaces of the nitride liners 204 a may be substantially the same. In example embodiments, in each of the isolation structures 208 a of the first to fourth peripheral regions A1, A2, B1, and B2, the uppermost surface of each of the nitride liners 204 a may be substantially coplanar with an upper surface of the substrate 100 adjacent to the nitride liner 204 a.

The first gate structure 260 a may include a first interface insulation pattern 224 a, a first high-k dielectric pattern 230 a, a first P-type metal pattern 232 a, a first N-type metal pattern 234 a, a first lower electrode 250 a, a first barrier pattern, a first upper electrode 254 a, and a first capping layer pattern 256 a sequentially stacked. The second gate structure 260 b may include a second interface insulation pattern 226 a, a second high-k dielectric pattern 230 b, a second P-type metal pattern 232 b, a second N-type metal pattern 234 b, a second lower electrode 250 b, a second barrier pattern, a second upper electrode 254 b, and a second capping layer pattern 256 b sequentially stacked.

A gate length of the first gate structure 260 a may be less than a gate length of the second gate structure 260 b. The gate length of the first and second gate structures 260 a and 160 b may be a line width of the gate structure.

A thickness of the first interface insulation pattern 224 a may be less than a thickness of the second interface insulation pattern 226 a. In example embodiments, a material of the first interface insulation pattern 224 a may be different from a material of the second interface insulation pattern 226 a. For example, the first interface insulation pattern 224 a may include silicon oxide, and the second interface insulation pattern 226 a may include silicon oxynitride.

The first and second gate structures 260 a and 260 b may have substantially the same stacked structure, except for the first and second interface insulation patterns 224 a and 226 a. That is, in the first and second gate structures 260 a and 260 b, a stacked structure formed on the first interface insulation pattern 224 a and a stacked structure formed on the second interface insulation pattern 226 a may be substantially the same. In the first and second gate structures 260 a and 260 b, the stacked structures formed on the first and second interface insulation patterns 224 a and 226 a may be substantially the same as the stacked structure formed on the first interface insulation pattern in the first gate structure described with reference to FIG. 1.

The third gate structure 260 c may include a third interface insulation pattern 224 b, a third high-k dielectric pattern 230 c, a third N-type metal pattern 234 c, a third lower electrode 250 c, a third barrier pattern, a third upper electrode 254 c, and a third capping layer pattern 256 c sequentially stacked. The fourth gate structure 260 d may include a fourth interface insulation pattern 226 b, a fourth high-k dielectric pattern 230 d, a fourth N-type metal pattern 234 d, a fourth lower electrode 250 d, a fourth barrier pattern, a fourth upper electrode 254 d, and a fourth capping layer pattern 256 d sequentially stacked.

A gate length of the third gate structure 260 c may be less than a gate length of the fourth gate structure 260 d. A thickness of the third interface insulation pattern 224 b may be less than a thickness of the fourth interface insulation pattern 226 b. In example embodiments, a material of the third interface insulation pattern 224 b may be different from a material of the fourth interface insulation pattern 226 b. For example, the third interface insulation pattern 224 b may include silicon oxide, and the fourth interface insulation pattern 226 b may include silicon oxynitride.

The third and fourth gate structures 260 c and 260 d may have the same stacked structure, except for the third and fourth interface insulation patterns 224 b and 226 b. That is, in the third and fourth gate structures 260 c and 260 d, a stacked structure formed on the third interface insulation pattern 224 b and a stacked structure formed on the fourth interface insulation pattern 226 b may be substantially the same. In the third and fourth gate structures 260 c and 260 d, the stacked structures formed on the third and fourth interface insulation patterns 224 b and 226 b may be substantially the same as the stacked structure formed on the second interface insulation pattern in the second gate structure described with reference to FIG. 1.

As described above, the bit line structure 280 in the cell array region CA may include a first structure in which the lower electrode, the barrier pattern, the upper electrode, and the capping layer pattern are stacked. In addition, in the first and second gate structures 260 a and 260 b, the first structure including the lower electrode, the barrier pattern, the upper electrode, and the capping layer pattern may be stacked on each of the first and second N-type metal patterns 234 a and 234 b. In the third and fourth gate structures 260 c and 260 c, the first structure including the lower electrode, the barrier pattern, the upper electrode, and the capping layer pattern may be stacked on each of the third and fourth N-type metal patterns 234 c and 234 d.

First to fourth spacers 262 a, 262 b, 262 c and 262 d may be formed on sidewalls of the first to fourth gate structures 260 a, 260 b, 260 c and 260 d, respectively. An insulating interlayer 266 may be formed to cover the first to fourth gate structures 260 a, 260 b, 260 c and 260 d.

An upper capping layer 270 may be formed on the insulating interlayer 266 in the first to fourth peripheral regions A1, A2, B1, and B2.

As described above, the DRAM cells may be formed in the cell array region CA. The low voltage PMOS transistor, the high voltage PMOS transistor, the low voltage NMOS transistor, and the high voltage NMOS transistors including high-k dielectric layers may be formed in the first to fourth peripheral regions A1, A2, B1, and B2. At least the low voltage PMOS transistor may be formed on the channel layer 130 including the silicon germanium. The isolation structure including the nitride liner 204 a having the protruding portion may be formed in the first to fourth peripheral regions A1, A2, B1, and B2. The uppermost surface of the nitride liner 204 a may be coplanar with the upper surface of the substrate 100 adjacent thereto.

FIG. 18 is a cross-sectional view of a semiconductor device in accordance with example embodiments. The semiconductor device in FIG. 18 may be substantially the same as the semiconductor device shown in FIG. 17, except for further including a second channel layer.

Referring to FIG. 18, a second channel layer 130 a may be further formed on the substrate 100 of the second peripheral region A2. The second channel layer 130 a may be formed of, e.g., silicon germanium. The second gate structure 260 b may be formed on the second channel layer 130 a. That is, the high voltage PMOS transistor may be formed on the second channel layer 130 a.

FIGS. 19 to 26 are cross-sectional views of stages in a method of manufacturing a semiconductor device in accordance with example embodiments.

Referring to FIG. 19, the substrate 100 may include the cell array region CA, the first peripheral region A1, the second peripheral region A2, the third peripheral region B1, and the fourth peripheral region B2. A portion of the substrate 100 may be etched to form the cell trench 92 and the peripheral trench 90. The cell trench 92 may have a width less than a width of the peripheral trench 90.

A preliminary isolation structure 207 a including a preliminary inner wall oxide pattern 201 a, a nitride liner 204 a, and a preliminary filling insulation pattern 205 a may be formed in the peripheral trench 90. In example embodiments, the cell trench 92 may be filled with the inner wall oxide pattern, and thus a cell isolation structure 201 including the inner wall oxide pattern may be formed. In some example embodiments, a portion of the cell trench 92 may be filled with the inner wall oxide pattern and the nitride liner.

Word lines buried in the substrate 100 may be formed in the cell array region CA. An ion implantation process may be performed to form impurity regions in the substrate 100 adjacent to both sides of the word line in the cell array region CA.

Referring to FIG. 20, a first insulation layer, a second insulation layer, and a third insulation layer may be sequentially stacked on an entire surface of the substrate 100 and the cell isolation structure 201. The first insulation layer, the second insulation layer, and the third insulation layer may be patterned to form a buffer layer 216 including a first insulation layer pattern 210, a second insulation layer pattern 212 and a third insulation layer pattern 214 in the cell array region CA.

A first mask pattern 218 may be formed on the substrate 100. The first mask pattern 218 may cover the cell array region CA and the second to fourth peripheral regions A2, B1, and B2, and may expose the first peripheral region A1. The first mask pattern 218 may be formed of, e.g., a silicon oxide layer.

When the first mask pattern 218 is formed by an etching process, upper portions of a preliminary inner wall oxide pattern 201 a and a preliminary filling insulation pattern in the preliminary isolation structure 207 a in the first peripheral region A1 may be only etched by over etching in the etching process. Thus, etched thicknesses of the preliminary inner wall oxide pattern 201 a and the preliminary filling insulation pattern 205 a may be decreased.

Therefore, the isolation structure 208 a including an inner wall oxide pattern 202 a, the nitride liner 204 a, and a filling insulation pattern 206 a may be formed in the first peripheral region A1. The nitride liner 204 a may protrude from upper surfaces of the inner wall oxide pattern 202 a and the filling insulation pattern 206 a.

The channel layer 130 may be formed on the substrate 100 of the first peripheral region A1 exposed by the first mask pattern 218. The channel layer 130 may be formed of, e.g., a silicon germanium layer. The channel layer 130 may be formed by a selective epitaxial growth (SEG) process.

In some example embodiments, the first mask pattern may expose the first and second peripheral regions A1 and A2. In this case, the channel layer may be formed on the substrate 100 of the first peripheral region A1 and the second peripheral region A2. Therefore, the semiconductor device shown in FIG. 18 may be manufactured by subsequent processes.

Referring to FIG. 21, a photoresist pattern 220 may be formed to cover the channel layer 130 and the isolation structure 208 a in the first peripheral region A1. Thereafter, the first mask pattern 218 may be removed.

When the first mask pattern 218 is removed by an etching process, upper portions of the preliminary inner wall oxide pattern 201 a and the preliminary filling insulation pattern 205 a in the preliminary isolation structure 207 a in the second to fourth peripheral regions A2, B1, and B2 may be only etched by overetching in the etching process. Thus, etched thicknesses of the preliminary inner wall oxide pattern 201 a and the preliminary filling insulation pattern 205 a may be decreased. Therefore, the isolation structure 208 a including the inner wall oxide pattern 202 a, the nitride liner 204 a, and the filling insulation pattern 206 a may be formed in each of the second to fourth peripheral regions A2, B1, and B2.

In the first to fourth peripheral regions A1, A2, B1, and B2, each of the isolation structures 208 a may include the inner wall oxide pattern 202 a and the nitride liner 204 a protruding from the filling insulation pattern 206 a. An uppermost surface of the inner wall oxide pattern 202 a may be lower than an uppermost surface of the nitride liner 204 a. Thus, the recessed portion 222 may be formed between the nitride liner 204 a and the substrate 100 adjacent the nitride liner 204 a.

In the isolation structures 208 a formed in the first to fourth peripheral regions A1, A2, B1, and B2, heights of upper surfaces of the nitride liners 204 a may be substantially the same. In example embodiments, in the isolation structures 208 a in the first to fourth peripheral regions A1, A2, B1, and B2, the uppermost surfaces of the nitride liners 204 a may be substantially coplanar with an uppermost surface of the substrate 100 adjacent thereto.

In example embodiments, in the isolation structures 208 a in the first to fourth peripheral regions A1, A2, B1, and B2, vertical levels of bottoms of the recessed portions 222 may be substantially the same.

FIGS. 22 and 23, a high voltage interface insulation layer 226 may be formed on the substrate 100 of the second and fourth peripheral regions A2 and B2. The high voltage interface insulation layer 226 may be formed of, e.g., silicon oxynitride.

A low voltage interface insulation layer 224 may be formed on the substrate 100 and the channel layer 130 in the first and third peripheral regions A1 and B1. The low voltage interface insulation layer 224 may be formed of, e.g., silicon oxide. The low voltage interface insulation layer 224 may be formed to have a thickness less than a thickness of the high voltage interface insulation layer 226.

A high-k dielectric layer 230 may be conformally formed over an entire surface of the substrate 100. The high-k dielectric layer 230 may be formed by a deposition process, e.g., chemical vapor deposition (CVD) or atomic layer deposition (ALD). A P-type metal layer 232 may be conformally formed on the high-k dielectric layer 230.

A second mask pattern may be formed on the P-type metal layer 232. The second mask pattern may cover the first and second peripheral regions A1 and A2, and the second mask pattern may expose the third and fourth peripheral regions B1 and B2 and the cell array region CA. The P-type metal layer in the cell array region CA and the third and fourth peripheral regions B1 and B2 may be removed using the second mask pattern as an etching mask. Thus, the high-k dielectric layer 230 may be exposed on the cell array region CA and the third and fourth peripheral regions B1 and B2. The removing process may include wet etching. An N-type metal layer 234 may be formed on the P-type metal layer 232 and the high-k dielectric layer 230.

FIG. 23 is an enlarged view of a portion “G” of FIG. 22.

Referring to FIG. 23, the high-k dielectric layer 230, the P-type metal layer 232, and the N-type metal layer 234 may be stacked on the first and second peripheral regions A1 and A2. The high-k dielectric layer 230 and the N-type metal layer 234 may be stacked on the third and fourth peripheral regions B1 and B2.

In FIG. 22, in order to simplify the drawing, the high-k dielectric layer 230, the P-type metal layer 232, and the N-type metal layer 234 in the first and second peripheral regions A1 and A2 may be illustrated as a first layer 240, and the high-k dielectric layer 230 and the N-type metal layer 234 in the third and fourth peripheral regions B1 and B2 and the cell array region CA may be illustrated as a second layer 242. After forming the first and second layers, recessed portions 222 of the isolation structure in the first to fourth peripheral regions A1, A2, B1 and B2 may have remaining inner spaces.

Referring to FIG. 24, a third mask pattern may be formed to cover the N-type metal layer 234 in the first to fourth peripheral regions A1, A2, B1, and B2. The third mask pattern may expose the cell array region CA. The N-type metal layer 234 and the high-k dielectric layer 230 in the cell array region CA may be removed using the third mask pattern. Then, the third mask pattern may be removed.

A lower electrode layer 250 may be formed over the entire surface of the substrate 100. Portions of the lower electrode layer 250, the buffer layer 216, and the substrate 100 in the cell array region may be etched to form a first opening. The first opening may correspond to a position for forming a bit line contact. In an etching process for forming the first opening, an upper portion of the cell isolation structure 201 may be removed together.

A polysilicon layer may be formed to fill the first opening, and the polysilicon layer may be planarized by a planarization process. Thus, a polysilicon pattern 252 may be formed in the first opening.

A barrier layer and an upper electrode layer 254 may be formed on the lower electrode layer 250 and the polysilicon pattern 252. A capping layer pattern 256 may be formed on the upper electrode layer 254. The capping layer pattern 256 may cover entire of the cell array region CA. In addition, the capping layer pattern 256 may be also disposed at portions for forming the first to fourth gate structures in the first to fourth peripheral regions A1, A2, B1, and B2.

Referring to FIG. 25, the upper electrode layer 254, the barrier layer, the lower electrode layer 250, the P-type metal layer 232, the N-type metal layer 234, the high-k dielectric layer 230, the high voltage interface insulation layer 226, and the low voltage interface insulation layer 224 in the first to fourth peripheral regions A1, A2, B1 and B2 may be etched using the capping layer pattern 256 as an etching mask to form the first to fourth gate structures 260 a, 260 b, 260 c and 260 d. First to fourth spacers 262 a, 262 b, 262 c, and 262 d may be formed on sidewalls of the first to fourth gate structures 260 a, 260 b, 260 c, and 260 d, respectively.

P-type impurities may be doped onto the substrate adjacent to the sidewalls of the first and second gate structures 260 a and 260 b to form first and second impurity regions 264 a and 264 b, respectively. N-type impurities may be doped onto the substrate adjacent to the sidewalls of the third and fourth gate structures 260 c and 260 d to form third and fourth impurity regions 264 c and 264 d, respectively.

An insulating interlayer 266 may be formed on the entire surface of the substrate 100 to cover the first to fourth gate structures 260 a, 260 b, 260 c, and 260 d. An upper portion of the insulating interlayer 266 may be planarized. An upper capping layer 270 may be formed on the capping layer pattern 256 in the cell array region CA and the insulating interlayer 266 in the first to fourth peripheral regions A1, A2, B1, and B2.

Referring to FIG. 26, the upper capping layer 270, the capping layer pattern 256, the upper electrode layer 254, the barrier layer, the lower electrode layer 250, and the polysilicon pattern 252 in the cell array region CA may be etched using a mask to form a bit line structure 280. A bit line spacer 282 may be formed on a sidewall of the bit line structure 280.

An insulation layer may be formed to fill a gap between bit line structures 280. Portions of the insulation layer and the buffer layer 216 may be etched to form a second opening exposing the surface of the substrate 100. A contact plug 284 may be formed to fill the second opening. An upper insulation pattern 286 may be formed between upper portions of adjacent contact plugs 284.

Referring to FIG. 17 again, a capacitor 290 may be formed on the contact plug 184.

As described above, the DRAM cells may be formed in the cell array region, and the low voltage PMOS transistor, the high voltage PMOS transistor, the low voltage NMOS transistor, and the high voltage NMOS transistor including the high-k dielectric layer may be formed in the first to fourth peripheral regions. At least the low voltage PMOS transistor may be formed on the channel layer including the silicon germanium.

By way of summation and review, example embodiments provide a semiconductor device having good electrical characteristics and high reliability. That is, in the semiconductor device, in accordance with example embodiments, an isolation structure may include a nitride liner having a protruding portion that defines a recessed portion with an increased width. A metal material may not remain in the recessed portion, thereby decreasing defects, e.g., due to residual metal materials in the recessed portion, in the semiconductor device.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. 

What is claimed is:
 1. A semiconductor device, comprising: a substrate including a first region and a second region; a first trench in the substrate, the first trench being on the first region; a second trench in the substrate, the second trench being on the second region; a first isolation structure filling the first trench, the first isolation structure including a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked; a second isolation structure filling the second trench, the second isolation structure including a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked; a first gate structure on the substrate, the first gate structure including a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region of the substrate; and a second gate structure on the substrate, the second gate structure including a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region of the substrate, wherein the first inner wall oxide pattern and the first liner are conformal on a surface of the first trench, the first liner protruding above uppermost surfaces of the first inner wall oxide pattern and the first filling insulation pattern, and wherein the second inner wall oxide pattern and the second liner are conformal on a surface of the second trench, the second liner protruding above uppermost surfaces of the second inner wall oxide pattern and the second filling insulation pattern.
 2. The semiconductor device as claimed in claim 1, wherein the first and second inner wall oxide patterns and the first and second filling insulation patterns include silicon oxide, and the first and second liners include silicon nitride.
 3. The semiconductor device as claimed in claim 1, wherein an uppermost surface of the first inner wall oxide pattern is lower than an upper surface of a first portion of the substrate adjacent to the first trench, and an uppermost surface of the second inner wall oxide pattern is lower than an upper surface of a second portion of the substrate adjacent to the second trench.
 4. The semiconductor device as claimed in claim 3, wherein the uppermost surface of the first inner wall oxide pattern and the uppermost surface of the second inner wall oxide pattern are substantially coplanar with each other.
 5. The semiconductor device as claimed in claim 1, wherein the first inner wall oxide pattern has a thickness of 200 angstroms or more in a vertical direction from the surface of the first trench, and the second inner wall oxide pattern has a thickness of 200 angstroms or more in the vertical direction from the surface of the second trench.
 6. The semiconductor device as claimed in claim 1, wherein an uppermost surface of the first liner is substantially coplanar with an upper surface of a first portion of the substrate adjacent to the first liner, and an uppermost surface of the second liner is substantially coplanar with an upper surface of a second portion of the substrate adjacent to the second liner.
 7. The semiconductor device as claimed in claim 1, wherein heights of uppermost surfaces of the first and second liners are substantially the same.
 8. The semiconductor device as claimed in claim 1, further comprising a channel layer including silicon germanium on the first region of the substrate, the first gate structure being on the channel layer.
 9. The semiconductor device as claimed in claim 1, further comprising: a first recessed portion between the first liner and a first portion of the substrate adjacent to the first liner, an inner width of the first recessed portion being greater than a height from a bottom of the first recessed portion to an uppermost surface of the first liner, and a second recessed portion between the second liner and a second portion of the substrate adjacent to the second liner, an inner width of the second recessed portion being greater than a height from a bottom of the second recessed portion to an uppermost surface of the second liner.
 10. The semiconductor device as claimed in claim 1, further comprising: a first recessed portion between the first liner and a first portion of the substrate adjacent to the first liner, a bottom of the first recessed portion including a flat surface; and a second recessed portion between the second liner and a second portion of the substrate adjacent to the second liner, a bottom of the second recessed portion including a flat surface.
 11. A semiconductor device, comprising: a substrate including a cell array region, a first peripheral region, and a second peripheral region; memory cells on the cell array region of the substrate; trenches in the first and second peripheral regions of the substrate; an isolation structure filling each of the trenches, the isolation structure including an inner wall oxide pattern, a nitride liner, and a filling insulation pattern sequentially stacked; a channel layer in the first peripheral region of the substrate, the channel layer including silicon germanium; a first gate structure on the channel layer, the first gate structure including a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked; and a second gate structure on the second peripheral region of the substrate, the second gate structure including a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked, wherein the inner wall oxide pattern and the nitride liner are conformal on surfaces of each of the trenches, the nitride liner protruding above upper surfaces of the inner wall oxide pattern and the filling insulation pattern.
 12. The semiconductor device as claimed in claim 11, wherein the memory cells include dynamic random-access memory (DRAM) cells, the DRAM cells including bit line structures.
 13. The semiconductor device as claimed in claim 12, wherein each of the bit line structures includes a first structure having a polysilicon pattern, a metal pattern, and a capping pattern, the first structure being on the first N-type metal pattern of the first gate structure, and on the second N-type metal pattern of the second gate structure.
 14. The semiconductor device as claimed in claim 11, wherein the inner wall oxide pattern has a thickness of 200 angstroms or more in a vertical direction from surfaces of each of the trenches.
 15. The semiconductor device as claimed in claim 11, wherein an uppermost surface of the nitride liner is coplanar with an upper surface of a portion of the substrate adjacent to the nitride liner.
 16. The semiconductor device as claimed in claim 12, further comprising a recessed portion between the nitride liner and a portion of the substrate adjacent to the nitride liner, an inner width of the recessed portion being greater than a height from a bottom of the recessed portion to an uppermost surface of the nitride liner.
 17. A semiconductor device, comprising: a substrate including a cell array region, a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region; memory cells on the cell array region of the substrate; trenches on first to fourth peripheral regions of the substrate; an isolation structure filling each of the trenches, the isolation structure including an inner wall oxide pattern, a nitride liner, and a filling insulation pattern sequentially stacked; a channel layer on the first peripheral region of the substrate, the channel layer including silicon germanium; a first gate structure on the channel layer, the first gate structure including a first interface insulation pattern, a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked; a second gate structure on the second peripheral region of the substrate, the second gate structure including a second interface insulation pattern, a second high-k dielectric pattern, a second P-type metal pattern, and a second N-type metal pattern sequentially stacked, and a thickness of the second interface insulation pattern being greater than a thickness of the first interface insulation pattern; a third gate structure on the third peripheral region of the substrate, the third gate structure including a third interface insulation pattern, a third high-k dielectric pattern, and a third N-type metal pattern sequentially stacked; and a fourth gate structure on the fourth peripheral region of the substrate, the fourth gate structure including a fourth interface insulation pattern, a fourth high-k dielectric pattern, and a fourth N-type metal pattern sequentially stacked, wherein the nitride liner is conformal on surfaces of each of the trenches, the nitride liner protruding above upper surfaces of the inner wall oxide pattern and the filling insulation pattern, and a height of an uppermost surface of the nitride liner is substantially the same in each of the trenches.
 18. The semiconductor device as claimed in claim 17, wherein the memory cells include dynamic random-access memory (DRAM) cells, the DRAM cells including bit line structures.
 19. The semiconductor device as claimed in claim 17, wherein the inner wall oxide pattern has a thickness of 200 angstroms or more in a vertical direction from a surface of each of the trenches.
 20. The semiconductor device as claimed in claim 17, wherein, in the isolation structure in each of the first to fourth peripheral regions, an uppermost surface of the inner wall oxide pattern extends to a same height. 